This project involves the building of a simple, extremely streamlined CPU. It was designed in the interests of smooth implementation, rather than accuracy, so there are certain inherent design flaws in it, mostly related to high-speed timing; for our purposes, however, it works quite well. I highly recommend reading this document carefully. If I saw a need to spend time writing something, it’ll probably help you. With that said, there are many ways to implement a design project, some of which are objectively better than what’s been tested, so keep an open mind.
I strongly advise you to write a testbench for each module, but the only ones which are strictly required will be listed in the deliverables section. You are going to need separate Block Designs for synthesis and simulation for the reasons described below in Simulation Considerations.
Also, read section XI of this document please. Those aren’t binding instructions, but will help you quite a bit should you choose to follow them. The goals of this project are:
- Develop high-level design skills while working on a relatively modestly sized system
- Practice creating, simulating, and synthesizing Vivado Block Designs
- Learn to use IP; both predefined Xilinx IP and your own packaged designs.
- Use Verilog to develop a register simulation
- Demonstrate the ability to perfect behavioral designs and multiplexing in Verilog (the
meaning of this will become clear later in this document)
- Understand the function and implementation of basic CPU arithmetic instructions
- 7-Segment Display Control and Clock Division
- Button Debouncing and Input Filtering