Design a circuit to produce a rectangular wave of period 100 µs and 60% duty cycle. Any capacitors used are constrained to the value of 1 nF./Explain why obtaining a duty cycle of 50% or less cannot be achieved using the ‘555’ circuit of FIGURE 2. Describe a method by which the circuit could be modified to give a duty cycle of less than 50%.

Essay Paper > Design a circuit to produce a rectangular wave of period 100 µs and 60% duty cycle. Any capacitors used are constrained to the value of 1 nF./Explain why obtaining a duty cycle of 50% or less cannot be achieved using the ‘555’ circuit of FIGURE 2. Describe a method by which the circuit could be modified to give a duty cycle of less than 50%.
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Design a circuit to produce a rectangular wave of period 100 µs and 60% duty cycle. Any capacitors used are constrained to the value of 1 nF./Explain why obtaining a duty cycle of 50% or less cannot be achieved using the ‘555’ circuit of FIGURE 2. Describe a method by which the circuit could be modified to give a duty cycle of less than 50%.2. Design a circuit to produce a rectangular wave of period 100 µs and 60% duty cycle. Any capacitors used are constrained to the value of 1 nF.
3. Explain why obtaining a duty cycle of 50% or less cannot be achieved using the ‘555’ circuit of FIGURE 2. Describe a method by which the circuit could be modified to give a duty cycle of less than 50%.
4. FIGURE 3 represents a ‘555’ timer used to control a process. The process should commence when the START switch is operated and then continue for a period of 15 seconds (T) or until the STOP switch is activated.
Design a circuit to meet this specification.
5. In FIGURE 4(a) the input voltage V in is swept from 0 to 5 V. The supply voltage is a single-rail 5 V. Explain the shapes of the output responses of the two op-amps shown in FIGURE 4(b).

[TABLE E gives some further information on these op-amps.]

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Design a circuit to produce a rectangular wave of period 100 µs and 60% duty cycle. Any capacitors used are constrained to the value of 1 nF./Explain why obtaining a duty cycle of 50% or less cannot be achieved using the ‘555’ circuit of FIGURE 2. Describe a method by which the circuit could be modified to give a duty cycle of less than 50%.
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6. Estimate the maximum frequency of a sinusoidal input signal of 10 mV peak, for distortion-free output, when applied to an op-amp circuit of closed-loop gain of 100, if the op-amp used is the:
a) TL072
b) TLV2362