Cadence Virtuoso Layout

Learning Goal: I’m working on a computer science project and need an explanation and answer to help me learn.

Important : the layout should be done in Cadence Virtuoso

Don't use plagiarized sources. Get Your Custom Essay on
Cadence Virtuoso Layout
Just from $13/Page
Order Essay

Details

For the following basic cells, draw the layout and verify the functionality by simulating the extracted netlist. You should strive to get as compact a layout as possible without violating the design rules. The bounding box of a layout is the smallest rectangle in which your layout can fit. In the lab report you must report the bounding box area (width x height) of each cell.

  • , simulation waveforms. For simulation results, zoom in/out appropriately so that we can clearly see the input stimuli and the output response.

 

1. inverter

2. 2-input NAND and 3. 2-input NOR

—————————————————————————————————————–

  • Lab report using the template provided. PDF only.
  • A compressed zip file (.tar.gz file) of the design folder of each cell in your lib directory. On Linux you can create a compressed archive of a folder as follows:
  • You can use the pre-drawn cells for PMOS (epm) and NMOS (enm) cells in the c5 library as the starting point for your layouts.
  • You can expand/flatten epm or enm cell by first selecting the cell and then pressing Shift-f.

prompt% tar czvf <folder>.tar.gz <folder>

Assuming your library name is cmoslib and your cellview name for the 2-input NAND gate is NAND2, then executing the following command will compress the NAND2 design folder.

prompt% tar czvf NAND2.tar.gz cmoslib/NAND2

Tips

  • You can use the pre-drawn cells for PMOS (epm) and NMOS (enm) cells in the c5 library as the starting point for your layouts.
  • You can expand/flatten epm or enm cell by first selecting the cell and then pressing Shift-f.