Objective: Need to model and simulate basic gates with Virtuoso and verify their functionality.
1. (10 pts.) Inverter Create a schematic diagram for a CMOS inverter and simulate its transient
behavior for three different capacitive loads: (1) Cload = 0.01pF; (2) Cload = 0.05pF; and (3)
Cload = 0.1pF. For each load capacitance, determine (a) the rise time (tr); (b) fall time (tf) of
the output voltage; and (c) the rise and fall propagation delays (tpdr and tpdf) of the inverter.
Assume the input fall and rise time to be 0.1ns. State these measured values in your report.
2. (10 pts.) 2-input NAND Gate Create a schematic diagram for a 2-input NAND gate and using pulse
sources (PULSE) for the two inputs, verify its truth table. Assume that the NAND gate drives a
load capacitance of 0.01pF at its output.
3. (10 pts.) 2-input NOR Gate Create a schematic diagram for a 2-input NOR gate and using pulse
sources for the two inputs, verify its truth table. Assume that the NOR gate drives a load
capacitance of 0.01pF at its output.
Deliverables (must be uploaded to Canvas course webpage by the deadline)
· A compressed zip file (.tar.gz file) containing all your schematic diagrams as well as the simulated
output. On linux you can create a compressed archive of a folder as follows:
prompt% tar czvf <folder>.tar.gz <folder>
For example, executing the following command will compress the inv folder you created.
prompt% tar czvf inv.tar.gz inv
1. Follow the steps provided in the Virtuoso tutorial as the starting point.
2. Do not discard your files. We will use use them in later assignments.